A memory module is a system, typically on a single circuit board, that includes a number of memory chips. Memory modules are often configured to include data lines that are divided so that any one or group of ones of data lines will access the memory chips, such as DRAMs (dynamic random access memory), individually for transferring memory data. The module can also include further lines, called first lines hereinafter, that simultaneously access all the semiconductor memory chips and, therefore, connect the latter to one another in parallel. Such first lines are, by way of example, address lines for communicating memory addresses and also control lines for communicating control commands such as reading, writing, activation or deactivation of memory cells.
On account of the parallel interconnection, each semiconductor memory chip receives the same command sequence. Only the memory contents that are communicated via the data lines leading to in each case only a single semiconductor memory chip are transferred in chip-specific fashion.
If an individual memory chip is intended to be selectively addressed, for example in order to read chip-specific data, conventionally the normal memory operation is interrupted and a special operating mode of the memory module is set, in which, for instance, chip-specific data such as test results of a chip test or the former position of the memory chip within a wafer or the batch number of the wafer that was processed in order to fabricate the memory chip are transferred. Such information is still of importance even after start-up of a memory module, in order, in the event of error clusters, to identify the identity of the error-susceptible semiconductor chips affected during fabrication in semiconductor memory chips of a multiplicity of produced memory modules. Such data are usually stored in the form of electrically one-time blowable fuses on each semiconductor chip and can later be retrieved at any point in time, but not during the normal operation of a memory module. One reason for this is that the control lines required for transferring such individual chip data, during the operation of a memory module, are already required for communicating control commands such as writing, reading, etc., or for transferring commands such as chip select, row address strobe, column address strobe, write enable, clock or clock enable and are not available for further operations. Any interrogation of chip-specific data would thus result in an interruption of the module operation.
Module-specific data containing chip-specific data can also be stored on a customary EEPROM (electrically erasable programmable read only memory) present in the memory module. However, the capacity thereof is often limited. Moreover, its content is predetermined from the outset for each repeated instance of starting operation. By way of example, the number of semiconductor memory chips and their memory capacity are stored in the EEPROM. This chip is not suitable for storing or retrieving more extensive, in particular variable, data.
Chip-specific data consequently have to be stored or retrieved via the first lines that are required during the normal operation of the memory module.
There are principally two types of memory modules that are customary, which differ with regard to their driving when a plurality of memory modules are used in memory slots of a superordinate memory unit. In a memory arrangement whose main board has a plurality of module slots fitted with memory modules, each semiconductor memory chip of each memory module must be addressable selectively with respect to the rest of the semiconductor memory chips, at least in order to write or read memory data during normal memory operation.
In the case of SDRAMs (synchronous dynamic random access memory), the memory chips of a single memory module are in each case connected in parallel, so that all the memory chips are in each case accessed simultaneously. For the selection of a specific memory module or module slot (or a specific module side in the case of two-bank modules), use is made of a signal “chip select” on the main board, as a result of which in each case all the memory chips of a specific memory module are driven simultaneously. The data exchange is effected synchronously, i.e., at regular time intervals that are oriented to the clock signal and amount to a multiple of the clock cycle time. In the event of all the memory chips of the memory module being accessed in parallel, the bus width of the module results from the bus width of a memory chip times the number of memory chips connected in parallel, in which case in some instances an additional semiconductor memory chip is additionally connected in parallel for the purpose of error correction. A distinction is made between SDR-SDRAMs (single data rate) and DDR-SDRAMs (double data rate) depending on whether only the rising or both the rising and the falling clock edges of the clock signal are utilized for data transfer.
On the main board, the memory modules are likewise connected in parallel with one another. The signal “chip select” serves for driving a specific memory module, as a result of which the data bus of in each case a single memory module is selected. The chip select signal limits the parallelism of the driving; as a result, all the memory chips of only a single memory module are driven in parallel with one another.
In the case of SDRAMs, the abovementioned chip-specific driving is not possible at least during the normal memory operation. This is already unsuccessful due to the module-internal connection in parallel of all the semiconductor memory chips.
The memory modules of the other design are called RDRAMs, named after the provider Rambus. In the case of the Rambus system, a plurality of memory modules that are inserted into module slots of a main board are connected in series. During the so-called initialization of a memory module or the totality of a plurality of memory modules, each memory chip receives a chip-specific memory identifier. This daisy chain initialization enables a direct driving of a specific memory chip. In this case, too, the memory chips of a memory module are connected in parallel with one another. Use is made of a data bus that has 16 data lines, for example, and is rather narrow in comparison with SDRAMs. For example, the data bus transports data blocks within 4 clock times (in a “burst 8 mode” in the case of DDR-SDRAMs). During the operation of an RDRAM, the data sent to a memory module are simultaneously transported to all the memory chips of the module. However, the processing or taking-up of the data occurs only in the addressed memory chip. The rest of the memory chips “eavesdrop” in this time but do not react actively.
Thus, in the case of RDRAMs, the chip-specific driving is effected via the control lines, to be precise exclusively for the purpose of storing and interrogating memory data. If the intention is additionally to interrogate chip-specific data, for instance test data of previous memory tests, the normal operation has to be interrupted. Furthermore, there is the major disadvantage that when a specific memory chip is being driven, the rest of the memory chips of the same module are paralyzed since they cannot be driven simultaneously via the same data bus of the memory module. In the case where a plurality of RDRAMs are cascaded on a main board, the further disadvantage arises that empty module slots that are not occupied have to be occupied by bridging modules because otherwise the temporal coordination of the data exchange collapses.